View CY2278APAC-3L_3863980.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

pentium ? /ii clock synthesizer/driver for mobile pcs with intel ? 82430tx and no sdram cy2278a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07211 rev. *a revised decemeber 07, 2002 8a features ? mixed 2.5v and 3.3v operation complete clock solution to meet requirements of mo- bile pentium ? and pentium ? ii motherboards ? seven cpu clock outputs (three at 3.3v, and four at 2.5v or 3.3v) with eight selectable clock frequencies. ? ten 3.3v synchronous pci clock outputs ? two 3.3v usb/ir clocks at 48 mhz ? one keyboard clock at 8 mhz ? one 2.5v ioapic clock at 14.318 mhz ? two 3.3v ref. clocks at 14.318 mhz dedicated power management for portable systems ? separate output enable pins for cpu, pci, and usb/ir clock sets ? free-running pci and cpu clocks (see options) factory-eprom programmable output drive and slew rate for emi customization custom configuration with factory-eprom program- mable cpu, pci, and usb/ir frequencies. low skew and low jitter outputs available in space-saving 48-pin tssop package functional description the cy2278a is a clock synthesizer/driver chip for pentium or pentium ii portable pcs designed with the 82430tx or sim- ilar core-logic chipsets. there are four options available as shown in the selector guide. the cy2278a outputs seven cpu clocks, three of which run at 3.3v and four run at either 2.5v or 3.3v, depending on the voltage applied on pin 42. there are ten pci clocks, running at one half the cpu clock frequency. free-running pci and cpu clocks are available as options shown in the selector guide. additionally, the part outputs two 3.3v usb/ir clocks at 48 mhz, one keyboard clock at 8 mhz, one 2.5v ioapic clock at 14.318 mhz, and two 3.3v reference clocks at 14.318 mhz. the cy2278 family contains several features for output flexi- bility and power control. the cpu, pci, usb and ir clock frequencies are all factory eprom-programmable. three hardware select inputs support eight cpu clock frequencies from 20 ? 75 mhz. additionally, each of the cpu, pci, and usb/ir clock sets can be turned on or off with a dedicated enable input pin for power management. the cy2278a outputs are designed for low emi emissions. controlled rise and fall times, unique output driver circuits and factory-eprom programmable output drive and slew-rate en- able optimal configurations for emi control. cy2278a selector guide notes: 1. one free-running cpu clock. 2. two free-running pci clocks. clock outputs -1l -2l -3l -4l cpu@3.3v 3333 cpu@2.5/3.3v 4 [1] 444 pci (cpu/2 mhz) 10 [2] 10 10 [2] 10 [2] usb/ir (48 mhz) 2222 kb (8 mhz) 1111 ioapic (14.318 mhz)2222 ref (14.318 mhz) 2222 cpu-pci delay 0 ns 0 ns 1 ? 5 ns 0 ns intel and pentium are registered trademarks of intel corporation. eprom logic block diagram x out x in ioapic osc. clk8mhz sel2 xcpuclk3_f pll0 usb_run pll1 /2 cpu_run pci_run ref[0-1] 2.5 ? 3.3v driver usbclk/irclk xcpuclk [0-2] cpuclk [0-2] pciclk [2-9] sel1 sel0 2.5 ? 3.3v driver 14.318 mhz 96 mhz 48 mhz 8 mhz d ck cpuclk pciclk /2 /12 d ck d ck pciclk_f [0-1] d ck d ck d ck on -1l only; not free- running on -2l, -3l, -4l running on -2l on -1l, -3l, -4l only; not free-
cy2278a document #: 38-07211 rev. *a page 2 of 12 pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 25 26 27 28 36 35 ref1 34 tssop top view 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 2278a-1l ref0 v ss x in x out v ddq3 pciclk0_f pciclk1_f v ss pciclk2 pciclk3 pciclk4 pciclk5 v ddq3 pciclk6 v ss pciclk7 pciclk8 v ddq3 pciclk9 clk8mhz v ddq3 usbclk irclk v ddq2 ioapic pwr_dwn v ss xcpuclk0 xcpuclk1 v ddcpu xcpuclk2 xcpuclk3_f v ss cpuclk0 cpuclk1 v ddq3 cpuclk2 sel0 v ss sel1 sel2 v ss cpu_run usb_run pci_run av dd v ss 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 25 26 27 28 36 35 ref1 34 tssop top view 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 2278a-2l ref0 v ss x in x out v ddq3 pciclk0 pciclk1 v ss pciclk2 pciclk3 pciclk4 pciclk5 v ddq3 pciclk6 v ss pciclk7 pciclk8 v ddq3 pciclk9 clk8mhz v ddq3 usbclk irclk v ddq2 ioapic pwr_dwn v ss xcpuclk0 xcpuclk1 v ddcpu xcpuclk2 xcpuclk3 v ss cpuclk0 cpuclk1 v ddq3 cpuclk2 sel0 v ss sel1 sel2 v ss cpu_run usb_run pci_run av dd v ss 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 25 26 27 28 36 35 ref1 34 tssop top view 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 2278a-3l ref0 v ss x in x out v ddq3 pciclk0_f pciclk1_f v ss pciclk2 pciclk3 pciclk4 pciclk5 v ddq3 pciclk6 v ss pciclk7 pciclk8 v ddq3 pciclk9 clk8mhz v ddq3 usbclk irclk v ddq2 ioapic pwr_dwn v ss xcpuclk0 xcpuclk1 v ddcpu xcpuclk2 xcpuclk3 v ss cpuclk0 cpuclk1 v ddq3 cpuclk2 sel0 v ss sel1 sel2 v ss cpu_run usb_run pci_run av dd v ss 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 25 26 27 28 36 35 ref1 34 tssop top view 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 2278a-4l ref0 v ss x in x out v ddq3 pciclk0_f pciclk1_f v ss pciclk2 pciclk3 pciclk4 pciclk5 v ddq3 pciclk6 v ss pciclk7 pciclk8 v ddq3 pciclk9 clk8mhz v ddq3 usbclk irclk v ddq2 ioapic pwr_dwn v ss xcpuclk0 xcpuclk1 v ddcpu xcpuclk2 xcpuclk3 v ss cpuclk0 cpuclk1 v ddq3 cpuclk2 sel0 v ss sel1 sel2 v ss cpu_run usb_run pci_run av dd v ss
cy2278a document #: 38-07211 rev. *a page 3 of 12 pin summary name pins description v ddq3 6, 14, 19, 22, 36 3.3v digital voltage supply v ddq2 48 ioapic digital voltage supply, 2.5v v ddcpu 42 cpu digital voltage supply, 2.5v or 3.3v av dd 26 analog voltage supply, 3.3v v ss 3, 9, 16, 25, 31, 33, 39, 45 ground xtalin [3] 4 reference crystal input xtalout [3] 5 reference crystal feedback sel2 30 cpu clock frequency select input, bit 2 sel1 32 cpu clock frequency select input, bit 1 sel0 34 cpu clock frequency select input, bit 0 pci_run 27 control input, stops all pci clocks except pciclk_f when driven low usb_run 28 control input, stops all usb/ir clocks when driven low cpu_run 29 control input, stops all cpu clocks except xcpuclk_f when driven low pwr_dwn 46 power down input, shuts down device when driven low xcpuclk[0:2] 44, 43, 41 2.5v or 3.3v cpu clock outputs xcpuclk3_f 40 2.5v or 3.3v cpu clock output, free-running on cy2278a-1l only. this output is not free-running on the -2l, -3l, -4l configurations. cpuclk[0:2] 38, 37, 35 3.3v cpu clock output pciclk[2:9] 10, 11, 12, 13, 15, 17, 18, 20 pci clock outputs pciclk_f[0:1] 7, 8 pci clock outputs, free-running on cy2278a-1l, -3l, -4l only. this output is not free-running on the -2l configuration clk8mhz 21 8-mhz keyboard clock output ioapic 47 ioapic clock output ref[0:1] 2, 1 reference clock outputs, 14.318 mhz. ref0 has high drive usbclk/irclk 23, 24 usb or ir clock outputs, 48 mhz function table sel2 sel1 sel0 xtalin cpuclk pciclk ref ioapic usbclk irclk clk8mhz 0 0 0 14.318 mhz 75.0 mhz 37.5 mhz 14.318 mhz 48.0 mhz 8.0 mhz 0 0 1 14.318 mhz 20.0 mhz 10.0 mhz 14.318 mhz 48.0 mhz 8.0 mhz 0 1 0 14.318 mhz 25 mhz 12.5 mhz 14.318 mhz 48.0 mhz 8.0 mhz 0 1 1 14.318 mhz 33.33 mhz 16.67 mhz 14.318 mhz 48.0 mhz 8.0 mhz 1 0 0 14.318 mhz 50.0 mhz 25.0 mhz 14.318 mhz 48.0 mhz 8.0 mhz 1 0 1 14.318 mhz 60.0 mhz 30.0 mhz 14.318 mhz 48.0 mhz 8.0 mhz 1 1 0 14.318 mhz 66.67 mhz 33.33 mhz 14.318 mhz 48.0 mhz 8.0 mhz 1 1 1 14.318 mhz 40.0 mhz 20.0 mhz 14.318 mhz 48.0 mhz 8.0 mhz note: 3. for best accuracy, use a parallel-resonant crystal, c load = 18 pf.
cy2278a document #: 38-07211 rev. *a page 4 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) supply voltage .................................................. ? 0.5 to +7.0v input voltage .............................................. ? 0.5v to v dd +0.5 storage temperature (non-condensing) ... ? 65 c to +150 c junction temperature............................................... +150 c package power dissipation.............................................. 1w static discharge voltage............................................ >2000v (per mil-std-883, method 3015, like v dd pins tied together) actual clock frequency values clock output target frequency (mhz) actual frequency (mhz) ppm cpuclk(0,0,0) 75.0 75.0 0 cpuclk(0,0,1) 20.0 19.979 ? 1057 cpuclk(0,1,0) 25 24.974 ? 1057 cpuclk(0,1,1) 33.33 33.298 ? 1107 cpuclk(1,0,0) 50.0 49.947 ? 1057 cpuclk(1,0,1) 60.0 60.0 0 cpuclk(1,1,0) 66.67 66.654 ? 171 cpuclk(1,1,1) 40.0 39.992 ? 196 usbclk [4] 48.0 48.008 167 clk8mhz 8.0 8.001 167 operating conditions [5] parameter description min. max. unit av dd , v ddq3 analog and digital supply voltage 3.135 3.465 v v ddcpu, v ddq2 cpu and ioapic supply voltage 2.375 2.625 v t a operating temperature, ambient 0 70 c c l max. capacitive load on xcpuclk, cpuclk, usbclk/irclk, clk8mhz, ref1, ioapic pciclk ref0 20 20 30 45 pf f (ref) reference frequency, oscillator nominal value 14.318 14.318 mhz t pu power-up time for all vdd's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms notes: 4. meets intel usb clock requirements. 5. electrical parameters are guaranteed with these operating conditions.
cy2278a document #: 38-07211 rev. *a page 5 of 12 electrical characteristics parameter description test conditions min. max. unit v ih high-level input voltage except crystal inputs [6] 2.0 v v il low-level input voltage except crystal inputs [6] 0.8 v v oh high-level output volt- age v ddcpu , v ddq2 = 2.375v i oh = 9 ma xcpuclk 2.0 v i oh = 13 ma ioapic v ol low-level output voltage v ddcpu , v ddq2 = 2.375v i ol = 13 ma xcpuclk 0.4 v i ol = 18 ma ioapic v oh high-level output volt- age v ddq3 , av dd , v ddcpu = 3.135v i oh = 23 ma xcpuclk 2.4 v i oh = 23 ma cpuclk i oh = 23 ma pciclk i oh = 23 ma usbclk i oh = 23 ma clk8mhz i oh = 23 ma ref0 i oh = 23 ma ref1 v ol low-level output voltage v ddq3 , av dd , v ddcpu = 3.135v i ol = 17 ma xcpuclk 0.4 v i ol =17 ma cpuclk i ol = 17 ma pciclk i ol = 17 ma usbclk i ol = 17 ma clk8mhz i ol = 17 ma ref0 i ol = 17 ma ref1 i ih input high current v ih = v dd ? 10 +10 a i il input low current v il = 0v 10 a i dd power supply current [7] v ddq3 = 3.465v, v in = 0 or v dd , loaded outputs, cpu clocks = 66.67 mhz 200 ma i dd power supply current [7] v ddq3 = 3.465v, v in = 0 or v dd , unloaded outputs 100 ma i dds power-down current current draw in power-down state 150 a notes: 6. crystal inputs have cmos thresholds. 7. power supply current will vary with number of outputs which are running. therefore, power supply current can be calculated wi th the following formula: to be determined.
cy2278a document #: 38-07211 rev. *a page 6 of 12 switching characteristics [8] parameter output description test conditions min. typ. max. unit t 1 all output duty cycle [9] t 1 = t 1a t 1b 45 50 55 % t 2 xcpuclk xcpu clock rising and falling edge rate between 0.4v and 2.0v for 2.5v clocks 0.6 4.0 v/ns t 2 cpuclk, ioapic cpu and ioapic clock rising and falling edge rate between 0.4v and 2.0v for 2.5v clocks between 0.4v and 2.4v for 3.3v clocks 0.8 4.0 v/ns t 2 pciclk pci clock rising and fall- ing edge rate between 0.4v and 2.4v 0.75 4.0 v/ns t 2 usbclk, clk8mhz usb, clk8mhz clock ris- ing and falling edge rate between 0.4v and 2.4v 0.8 4.0 v/ns t 2 ref0 ref0 clock rising and falling edge rate between 0.4v and 2.4v 0.6 4.0 v/ns t 2 ref1 ref1 rising and falling edge rate between 0.4v and 2.4v 0.5 2.0 v/ns t 3 xcpuclk xcpu clock rise time between 0.4v and 2.0v 0.4 2.67 ns t 3 cpuclk ioapic cpu and ioapic clock rise time between 0.4v and 2.4v for 3.3v clocks between 0.4v and 2.0v for 2.5v clocks 0.5 0.4 2.5 2.0 ns t 3 pciclk pci clock rise time between 0.4v and 2.4v 0.5 2.67 ns t 3 usbclk, clk8mhz usb clock and clk8mhz rise time between 0.4v and 2.4v 2.5 ns t 4 xcpuclk xcpu clock fall time between 2.0v and 0.4v 0.4 2.67 ns t 4 cpuclk, ioapic cpu and ioapic clock fall time between 2.4v and 0.4v for 3.3v clocks between 2.0v and 0.4v for 2.5v clocks 0.5 0.4 2.5 2.0 ns t 4 pciclk pci clock fall time between 2.4v and 0.4v 0.5 2.67 ns t 4 usbclk, clk8mhz usb clock and i/o clock fall time between 2.4v and 0.4v 2.5 ns t 5 xcpuclk, cpuclk xcpu-xcpu clock skew cpu-cpu clock skew measured at 1.25v for 2.5v clocks measured at 1.5v for 3.3v clocks 100 300 250 ps t 5 pciclk pci-pci clock skew measured at 1.25v for 2.5v clocks, and at 1.5v for 3.3v clocks 500 ps t 6 xcpuclk, pciclk xcpu-pci clock skew measured at 1.25v for 2.5v clocks, and at 1.5v for 3.3v clocks (-1l, -2l, -4l con- figurations) 500 ps t 6 xcpuclk, pciclk xcpu-pci clock skew measured at 1.25v for 2.5v clocks, and at 1.5v for 3.3v clocks (-3l configuration) 1 3 5 ns t 7 xcpuclk, cpuclk cpu-xcpu clock skew measured at 1.25v for 2.5v clocks, and at 1.5v for 3.3v clocks 750 ps t 8 xcpuclk, cpuclk cycle-cycle clock jitter [10] measured at 1.25v for 2.5v clocks, and at 1.5v for 3.3v clocks 400 ps t 8 usbclk, pciclk cycle-cycle clock jitter measured at 1.5v 500 ps t 8 clk8mhz cycle-cycle clock jitter measured at 1.5v 650 ps t 9 xcpuclk, pciclk, cpuclk power-up time cpu, pci clock stabilization from power-up 3 ms notes: 8. all parameters specified with loaded outputs;sel[2:0] = 110. 9. duty cycle is measured at 1.5v when v dd = 3.3v. when v ddcpu = 2.5v, cpuclk duty cycle is measured at 1.25v. 10. room temperature.
cy2278a document #: 38-07211 rev. *a page 7 of 12 switching waveforms duty cycle timing t 1a t 1b output all outputs rise/fall time output t 2 t 3 v dd 0v t 2 t 4 xcpu-cpu clock skew t 5 xcpuclk ? cpuclk xcpu-pci clock skew xcpuclk t 6 , t 7 pciclk
cy2278a document #: 38-07211 rev. *a page 8 of 12 cpu_run timing [11, 12] pci_run timing [13, 14] usb_run timing [15] pwr_dwn timing notes: 11. cpuclk on and cpuclk off latency is two or three external cpuclk cycles. 12. cpu_run may be applied asynchronously. it is synchronized internally. 13. pciclk on and pciclk off latency is one rising edge of the external pciclk. 14. pci_run may be applied asynchronously. it is synchronized internally. 15. usbclk on and usbclk off latency is two usbclk cycles. switching waveforms (continued) cpuclk/ xcpuclk (internal) pciclk (internal) pciclk (free-running) cpu_run cpuclk (external) xcpuclk_f (free-running) pciclk (internal) pciclk pci_run pciclk (external) (free-running) usbclk (internal) usb_run usbclk (external) cpuclk (internal) pciclk (internal) pwr_dwn pciclk cpuclk (external) (external) vco crystal shaded section on the vco and crystal waveforms indicates that the vco and crystal oscillator are active, and there is a valid clock.
cy2278a document #: 38-07211 rev. *a page 9 of 12 application information clock traces must be terminated with either series or parallel termination, as is normally done. application circuit summary a parallel-resonant crystal should be used as the reference to the clock generator. the operating frequency and c load of this crystal should be as specified in the data sheet. optional trimming capacitors may be needed if a crystal with a different c load is used. footprints must be laid out for flexibility. surface mount, low-esr, ceramic capacitors should be used for filtering. typically, these capacitors have a value of 0.1 f. in some cases, smaller value capacitors may be required. the value of the series terminating resistor satisfies the following equation, where r trace is the loaded characteristic impedance of the trace, r out is the output impedance of the clock generator (specified in the data sheet), and r series is the series terminating resistor. r series > r trace ? r out footprints must be laid out for optional emi-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. typical values of these capacitors range from 4.7 pf to 22 pf. a ferrite bead may be used to isolate the board v dd from the clock generator v dd island. ensure that the ferrite bead offers greater than 50 ? impedance at the clock frequency, under loaded dc conditions. please refer to the application note ? layout and termination techniques for cypress clock generators ? for more details. if a ferrite bead is used, a 10 f ? 22 f tantalum bypass capacitor should be placed close to the ferrite bead. this capacitor prevents power supply droop during current surges.
cy2278a document #: 38-07211 rev. *a page 10 of 12 test circuit 3 6 9 0.1 f 14 16 v ddq3 c load outputs 39 26 45 0.1 f note: all capacitors should be placed as close to each pin as possible. 0.1 f 19 22 36 33 30 48 0.1 f 0.1 f 0.1 f v ddq2 0.1 f v ddcpu 42 0.1 f 25 ordering information ordering code package name package type operating range cy2278apac-1l z48 48-pin tssop commercial cy2278apac-2l z48 48-pin tssop commercial CY2278APAC-3L z48 48-pin tssop commercial cy2278apac-4l z48 48-pin tssop commercial
cy2278a document #: 38-07211 rev. *a page 11 of 12 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 48-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z48 51-85059-b
cy2278a document #: 38-07211 rev. *a page 12 of 12 document title: cy2278a pentium ? /ii clock synthesizer/driver for mobile pcs with intel ? 82430tx and no sdram document number: 38-07211 rev. ecn no. issue date orig. of change description of change ** 111728 12/15/01 dsg change from spec number: 38-00619 to 38-07211 *a 121844 12/14/02 rbi power up requirements added to operating conditions information

▲Up To Search▲

Price & Availability of CY2278APAC-3L

	To Download CY2278APAC-3L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .